The present invention relates firstly to a read/write amplifier for a DRAM memory cell in accordance with claim 1. Furthermore, the invention relates to a DRAM memory in accordance with claim 10. Finally, the invention also relates to a method for evaluating DRAM memory cells of a DRAM memory.
DRAM memory cells (Dynamic Random Access Memory cells) and memories represent an important type of memory for storing digital information. A DRAM is a memory in which, after specification of an address, data can be stored and read out again under this address. In DRAM memory cells and memories, respectively, the information is not stored as a switching state of a circuit but rather as a quantity of charge on a capacitance. Consequently, such a memory cell can be formed with only a storage capacitor and a selection transistor. Since every capacitor has leakage currents and leakage currents also flow via the selection transistor, the information in the DRAM memory cell is continuously degraded. The information content of the memory cell is therefore lost over time. In order to avoid this, the contents of the memory cells are periodically read out, the memory contents are evaluated and the memory cell is written to anew. This means that the charge contents of the storage capacitors are refreshed again, which is referred to as xe2x80x9crefreshxe2x80x9d.
DRAM memory cells are usually interconnected to form memory cell arrays, a DRAM memory having one or a plurality of such memory cell arrays. Each memory cell is connected, or wired, to the cell periphery via at least one word line and a bit line, the word line(s) and the bit line being routed via the memory cell and being oriented at least substantially perpendicularly to one another. Through activation of a specific word line, all the memory cells connected thereto can, via their bit lines, be read, written to or refreshed with regard to their information content.
In DRAM memory cells, digital information items can be stored for example in the form of logic xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d. Each of these logic information items is assigned a specific voltage value. By way of example, the voltage value for logic xe2x80x9c0xe2x80x9d may be zero volts, while the voltage value for logic xe2x80x9c1xe2x80x9d is 2 volts, for example. Before the memory cells are read, a reference voltage, for example a voltage of 1 volt is applied to all the bit lines. During the reading of the memory cell, the voltage value will either increase somewhat or else decrease, depending on the information content of the memory cell. This voltage change is compared with a reference voltage prevailing on a reference bit line. In this case, the reference bit line is connected to a memory cell which is currently not being evaluated. If the voltage value on the bit line that is to be evaluated is higher than the reference voltage, the information content logic xe2x80x9c1xe2x80x9d had been written to the memory cell. In the case of smaller voltage values, the information logic xe2x80x9c0xe2x80x9d had been written to the memory cell. The voltage signal read from the bit line to be evaluated and the reference bit line is conditioned and processed further, for example amplified, in a read/write amplifier.
Depending on the memory architecture, the bit lines (BL) of the memory cells to be evaluated and the respective reference bit lines (BBL) may be arranged beside one another in one and the same memory cell array and thus form a bit line pair in each case. In other memory architectures, the reference bit lines are each situated in a different memory cell array.
As has already been mentioned, the logic information items xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d are stored in the form of charge in cell capacitances in the case of a DRAM memory. These charges are converted into a small voltage signal in a first section of the evaluation. The read/write amplifier circuit of a DRAM memory has the task of amplifying this voltage signal to a full level. The amplified signal serves, on the one hand, for writing back the information that was destroyed in the memory cell during read-out, and, on the other hand, for forwarding the information read to the DRAM periphery. The read/write amplifier circuit must perform the aforementioned tasks with high evaluation reliability and speed in conjunction with the smallest possible space requirement.
Conventional read/write amplifier circuits generally comprise a number of components for assessing, amplifying and forwarding voltage signals read from the bit lines and reference bit lines.
These components include, for example, at least one xe2x80x9cN latch circuitxe2x80x9d (NL), which serves for producing the low level for the voltage value. The N latch circuit has the task of amplifying a voltage signal to this low level. With reference to the numerical example mentioned further above the low level might be, for example, the xe2x80x9c0xe2x80x9d volts value.
Furthermore, the read/write amplifier may have at least one xe2x80x9cP latch circuitxe2x80x9d (PL), which serves for producing a high level. Thus, the P latch circuit serves for amplifying a voltage signal to this high level, which corresponds to the xe2x80x9c2xe2x80x9d volts value, for example, in connection with the numerical example mentioned above.
A further component for the read/write amplifier is, for example, the xe2x80x9cequalizerxe2x80x9d (EQ), which serves for producing a reference voltage value (precharge level) on the bit lines.
Furthermore, the read/write amplifier may have at least one xe2x80x9cbit switchxe2x80x9d (BS), which is used for connecting a bit line pairxe2x80x94selected for example by a xe2x80x9ccolumn addressxe2x80x9dxe2x80x94to external data lines.
Finally, the read/write amplifier may have one or more transistors for changing over between different bit lines. Such transistors are, for example, selection transistors (MUX) for multiplexing the read/write amplifiers between different bit line pairs.
The individual components of the read/write amplifier will be explained in more detail in the further course of the description.
FIG. 1 diagrammatically illustrates a DRAM memory which is known from the prior art and in which different read/write amplifier circuits (SA) are utilized for bit line pairs of adjacent memory cell arrays (Arrays). Such read/write amplifier circuits are also referred to as xe2x80x9cshared sense amplifierxe2x80x9d. An arrangement of the different read/write amplifier circuits as illustrated in FIG. 1 already leads to a favorable ratio of the area proportions of memory cells and read/write amplifier circuits.
Depending on the DRAM memory type, the area required by the read/write amplifier circuit(s) can vary greatly in relation to the total area of the memory. The absolute area of a read/write amplifier circuit usually remains the same, so that the relative size of the read/write amplifier circuit in the overall memory changes depending on the memory architecture. In this case, the relative size of the read/write amplifier circuits in a DRAM memory may be between 5% and 30% of the total memory area. There is, therefore, a need to minimize the required area of the read/write amplifier circuits as well as possible.
In a known DRAM memory, with the aid of a second metal plane in the integrated circuit per memory cell array, it is possible to evaluate an additional bit line pair with each read/write amplifier circuit. This architecture thus halves the required number of read/write amplifier circuits in comparison with a conventional memory architecture as described above. However, the use of two metal planes is very cost-intensive and hence disadvantageous.
Another approach which is known from the prior art and serves for saving read/write amplifier area consists in the multiple use of the same read/write amplifier for different bit line pairs by multiplexing. Such an approach is illustrated for example in FIG. 2 and is explained in more detail in the context of the description of the figures. This known principle is based on the multiple utilization of read/write amplifier circuits for bit line pairs in the same memory cell array. The read/write amplifier (SA) is connected by selection transistors (MUX) to respectively complementary halves of bit line pairs of a cell array. The connected bit line pairs can be evaluated in a customary manner. An unamplified voltage signal develops on the unconnected bit line pairs. The voltage signal must remain undisturbed until the read/write amplifier circuit is changed over to the corresponding bit lines. The signal amplification and the writing back to the memory cells can then take place. During this second phase, the amplified voltage levels must remain on the bit lines evaluated in the first step. If the aforementioned preconditions are met, then at the end of the second phase the read-out information items of the entire cell array are written back and the word line can be deactivated.
One disadvantage of this solution approach, however, resides in the expected high degree of interference with the voltage signal on the unconnected bit lines as a result of capacitive overcoupling of the voltage changes on the adjacent bit lines which are connected to the read/write amplifier circuits. This interference can become so great that the voltage changes caused thereby no longer permit error-free evaluation of the memory cells.
Furthermore U.S. Pat. No. 4,916,667 discloses a DRAM memory in which an equalize component is assigned to a first bit line pair and the bit switch component is assigned to a second bit line pair, in which case the first bit line pair and the second bit line pair can be interconnected.
U.S. Pat. No. 5,757,692 describes a further semiconductor memory.
Taking the abovementioned prior art as a departure point, the present invention is based on the object of providing a read/write amplifier, a DRAM memory and also a method for evaluating DRAM memory cells of a DRAM memory with which the abovementioned disadvantages are avoided. In particular, the intention is that the read/write amplifier circuit can perform the tasks intended for it with high evaluation reliability and speed in conjunction with the smallest possible space requirement.
This object is achieved by means of the read/write amplifier for a DRAM memory cell in accordance with patent claim 1, the DRAM memory in accordance with patent claim 10 and also the method for evaluating DRAM memory cells of a DRAM memory in accordance with patent claim 15. Further, advantageous features, aspects and details of the invention emerge from the dependent claims, the description and the drawings. Advantages and features which are described with regard to the read/write amplifier likewise apply to the DRAM memory and also the method. Advantages and features which are described with regard to the DRAM memory likewise apply to the read/write amplifier according to the invention and also the method according to the invention. The same applies analogously to the method according to the invention.
The first aspect of the present invention provides a read/write amplifier for a DRAM memory cell, which, for evaluation of the information content of at least one DRAM memory cell, is connected or can be connected to at least one bit line and to at least one reference bit line, which in each case form a bit line pair. The read/write amplifier has a number of components for assessment, amplification and forwarding of voltage signals read from the bit lines and reference bit lines. According to the invention, this read/write amplifier is characterized in that it has a first read/write amplifier element and a second read/write amplifier element separate therefrom, and in that the individual amplifier components are divided between the two read/write amplifier elements.
This produces an area-optimized DRAM read/write amplifier circuit which has only a small space requirement and with which the evaluation of DRAM memory cells, in particular of memory cells of a single memory cell array, can be evaluated with high reliability and speed.
The read/write amplifier according to the invention makes it possible to avoid the problems outlined with respect to the prior art on account of the fact that the individual components of the read/write amplifier can be used for a plurality of bit line pairs in a memory cell array and with simultaneous direct amplification of all the signals being made possible.
A basic concept of the present invention is that the individual components of the read/write amplifier circuit are now divided between two read/write amplifier elements. These two read/write amplifier elements are embodied separately from one another. The first read/write amplifier element (SAINT) serves primarily for writing back cell information items, while the second read/write amplifier element (SAEX) can additionally drive the information item read out, or the datum read out, into an external area of the DRAM memory and enables the writing of cell information items.
Since a plurality of bit lines, or bit line pairs, can now be evaluated by one and the same read/write amplifier which has merely been divided between two amplifier elements, the requisite space requirement for the read/write amplifier circuits in the entire DRAM memory can be considerably reduced.
In the light of the present invention, evaluation of a memory cell is understood to be not only the reading of information items from a memory cell but also the forwarding of the information and also the subsequent writing back of the cell information at the end of the evaluation operation.
For the mode of operation of the read/write amplifier according to the invention, reference is likewise made to the explanations regarding the method according to the invention.
The amplifier components may advantageously have at least one N latch circuit for amplifying a voltage signal to a low level and/or at least one P latch circuit for amplifying a voltage signal to a high level and/or at least one equalizer for producing a reference voltage value on the bit line(s) and the reference bit line(s) and/or at least one bit switch for connecting at least one selected bit line pair to at least one external data line.
Preferably, at least one N latch circuit and at least one P latch circuit may be provided in the first read/write amplifier element.
Furthermore, the first read/write amplifier element may be provided with at least one equalizer. The function of the equalizer is to set the voltage signals amplified to low levels and/or high levels after the evaluation operation once again to the reference voltage value.
At least one N latch circuit may advantageously be provided in the second read/write amplifier element.
Furthermore, at least one bit switch may be provided in the second read/write amplifier element. If only the second read/write amplifier element is provided with a bit switch, in each case only half of the memory cells activated by a word line can potentially be read or written to anew. In this case, the bit switch has the following basic function. If a specific memory cell is intended to be read, the entire page, that is to say the quantity of all the memory cells which are connected to a word line, is addressed in which said memory cell is situated. This means that the information items of the entire page are read out. By means of activation of the bit switch, that/those memory cell(s) whose information content is actually of interest can now be selected from the entire quantity of the memory cells read.
In a further refinement, it is possible that the second read/write amplifier element is connected or can be connected to at least one external data line. These external data lines lead from the evaluated DRAM memory cell, or the memory cell array, through to the DRAM memory periphery.
It is advantageously possible that the second read/write amplifier element is connected or can be connected to at least one further read/write amplifier. This additional read/write amplifier, also called xe2x80x9cSecondary Sense Amplifier (SSA)xe2x80x9d can further amplify the voltage signals that have been read from the read/write amplifier assigned to the DRAM memory and have been correspondingly amplified, with the result that these voltage signals can also be utilized further outside the DRAM memory.
The first and/or the second read/write amplifier element may have one or more transistors for changing over between different bit lines and reference bit lines, respectively. These transistors, which, for example, are also called selection transistors or multiplex transistors, determine which bit line pair is actively connected to the first and/or second read/write amplifier element.
A second aspect of the present invention provides a DRAM memory, having a number of DRAM memory cells, which each form one or more memory cell arrays, each memory cell being connected to a bit line and the bit lines furthermore being connected to at least one read/write amplifier. The invention provides for the at least one read/write amplifier to be designed as a read/write amplifier according to the invention as described above.
A DRAM memory according to the invention, designed in this way, makes it possible for the individual memory cells to be evaluated with high evaluation reliability and speed in conjunction with a very small space requirement of the read/write amplifier circuits and hence of the DRAM memory. For the mode of operation of the DRAM memory according to the invention, reference is likewise made to the explanations concerning the method according to the invention.
At least one word line may advantageously be provided, which is routed across the memory cell array(s) of the DRAM memory and, for activation of the DRAM memory cells, is connected to one or more memory cell(s). In this case, the at least one physical word line can be divided by the selection transistors into two logical word lines. The cell signals of one word line half are amplified by the first read/write amplifier element, while the cell signals of the other word line half are amplified by the second read/write amplifier element.
Preferably, a plurality of bit lines of a memory cell array are connected to the read/write amplifier.
In each case a bit line of a DRAM memory cell that is to be evaluated and a reference bit line of a DRAM memory cell that is not to be evaluated may form a bit line pair, each bit line pair being connected both to the first and to the second read/write amplifier element.
It may be the case here that the connection of a bit line and/or reference bit line to the read/write amplifier is activated or can be activated preferably via one or more transistors.
A third aspect of the present invention provides a method for evaluating DRAM memory cells of a DRAM memory, in particular of a DRAM memory according to the invention as described above, and in particular using a read/write amplifier according to the invention as described above, which method has the following steps.
Firstly, one or a plurality of memory cell(s) to be evaluated is/are activated via at least one word line. If a plurality of memory cells are intended to be evaluated, they are preferably situated within a single memory cell array. The memory cells connected to the word line can be read through the activation of said word line.
Afterward, the connection of at least one first bit line pair, formed from a bit line of the memory cell that is to be evaluated and a reference bit line of a memory cell that is not to be evaluated, to a first read/write amplifier element is activated and, at the same time, the connection of at least one second bit line pair, adjacent to the first bit line pair, to a second read/write amplifier element is activated, the two bit line pairs in each case being connected to the first and second read/write amplifier elements.
If the read/write amplifier is connected for example to two bit line pairs, that is to say each of the two read/write amplifier elements is in each case connected to both bit line pairs, the transistors may initially be switched in such a way that one of the two bit line pairs is actively coupled to the first read/write amplifier element, while the other bit line pair is actively coupled to the second read/write amplifier element.
The voltage signals read out via the first bit line pair are subsequently amplified by means of at least one N latch circuit provided in the first read/write amplifier element and also a P latch circuit. At the same time, the voltage signals read out via the second bit line pair are amplified by means of at least one N latch circuit provided in the second read/write amplifier element. This is done, for example, as follows.
At the beginning of the evaluation, a reference voltage is applied preferably to all of the bit lines. If the cells to be read are activated, the voltage value present on the bit line to be evaluated changes as a result of the activation. By way of example, the voltage value rises slightly in the case of an information item of logic xe2x80x9c1xe2x80x9d situated in the memory cell whereas it falls slightly in the case of a logic information item xe2x80x9c0xe2x80x9d stored in the memory cell. In the case of the unactivated reference bit line, however, the voltage value remains substantially constant. By comparison between the bit line (BL) and the reference bit line (BBL), it is now possible to see what information had been stored in the memory cell, depending on whether the voltage value read out lies above or below the reference voltage value.
The cell signals of the memory cells connected to the second read/write amplifier element, or the voltage values read out via the corresponding bit lines, are initially amplified only by means of an N latch circuit. If an information item logic xe2x80x9c0xe2x80x9d had been stored in the memory cell to be evaluated, this means that the voltage value present on the bit line to be read at the beginning of the evaluation is less than the reference voltage value on the reference bit line. The N latch circuit amplifies to the low level the voltage values of those bit lines which have a lower voltage value. In this case, this means that the memory cell having the information item logic xe2x80x9c0xe2x80x9d is amplified down to the low level. The voltage signal of the reference bit line initially remains substantially unchanged, or falls significantly less than the voltage signal of the bit line.
If an information item logic xe2x80x9c1xe2x80x9d had been situated in the memory cell to be evaluated, this would have led to a slight voltage increase relative to the reference voltage value. The N latch circuit would once again have amplified the lower of the two voltage values down to a low level. In this case, this would have been the voltage value on the reference bit line. From the substantially unchanging voltage value, or voltage value falling to a significantly lesser degree, of the bit line to be evaluated, it would then have been possible to infer that the information content stored in the memory cell to be evaluated is logic xe2x80x9c1xe2x80x9d.
Also by using only a single N latch circuit in the second read/write amplifier element, it is possible, during the first amplification step, to state exactly what kind of information item had been stored, or is stored, in the memory cells. If the voltage value on the bit line to be evaluated is pulled down to a low level, it is known that the information in the memory cell was logic xe2x80x9c0xe2x80x9d. However, if the voltage value of the reference bit line is pulled down to a low level, it is known that the information in the memory cell was logic xe2x80x9c1xe2x80x9d.
At the same time as the amplification in the second read/write amplifier element, the memory cells connected to the first read/write amplifier element are also evaluated. In addition to the N latch circuit, however, the first read/write amplifier element also has a further P latch circuit. As has been described above with regard to the second read/write amplifier element, the respective lower voltages in a bit line pair are amplified to the low level. The respective other cell signals, that is to say the higher voltage signals, are amplified to the full high level by means of the P latch circuit. This means that if the voltage value on the bit line of the memory cell to be evaluated has been amplified down to a low level, the voltage value present on the reference bit line is amplified to the high level.
In principle, voltage signals amplified to both levels are required in order to be able subsequently to write back to the memory cells. This means that the voltage values initially not amplified to high levels in the second read/write amplifier element also still have to be amplified in a corresponding manner.
After the voltage signals have been amplified in the above way, the data of the memory cell(s) that is/are to be evaluated and is/are actively connected to the first read/write amplifier element are evaluated and subsequently written back. After the writing back of the data by the first read/write amplifier element, the corresponding bit line pairs can be disconnected by the selection transistors, with the result that they float at full voltage levels.
The connection between the bit line pairs and the first read/write amplifier element is subsequently changed over in such a way that the P latch circuit of the first read/write amplifier element is now changed over to the second read/write amplifier element.
The N latch circuit of the first read/write amplifier element is then switched off, while the still active P latch circuit is coupled to the bit line pair connected to the second read/write amplifier element. As a result, the voltages of the bit line pair that have hitherto not been amplified to high levels can be amplified to a full level. In this case, the N latch circuit of the second read/write amplifier element is likewise held active.
The data of the memory cell(s) that is/are to be evaluated and is/are actively connected to the second read/write amplifier element are subsequently evaluated and written back.
Afterward, in order to end the evaluation method, the memory cells that are to be evaluated can be deactivated.
There is no loss of time caused by the successive amplification to the high level of the individual bit line pairs by only a single P latch circuit, since the cell information items can already be output to the outside via the second read/write amplifier element before both levels, that is to say the low level and also the high level, are fully installed.
Before the evaluation of the memory cells, a uniform reference voltage can be applied to all the bit lines of the memory cells provided in one or more memory cell arrays. The generation and the function of such a reference voltage have been thoroughly explained further above.
Preferably, after the activation of a bit switch provided in the second read/write amplifier element, a voltage difference can be generated on one or more external data line(s) connected to said bit switch.
This voltage difference can then be evaluated by a further, external read/write amplifier.
After the end of the evaluation operation, the uniform reference voltage may advantageously be applied to all the bit lines of the evaluated memory cells via an equalizer.